1. Technical Field of the Invention
The present invention relates to trace routing topologies and, more particularly, to topologies that allow for identical connection point layouts on primary and secondary sides of a substrate.
2. Background Art
Some processors, such as microprocessors, utilize an off-chip cache chip (sometimes called L2 caches) to hold data for use by a processor chip of the processor. The cache chip is mounted on a substrate such as a printed circuit board and is connected to processor core chip through a high speed bus.
For example, the Pentium.RTM. II processor manufactured by Intel Corporation includes a substrate to which a processor chip and a cache chip are connected. The substrate includes connector points that are mated with connector points on the processor chip and cache chip to connect the processor chip and cache chip to the substrate. The substrate includes multiple layers. Traces are connected to the connector points of the substrate to couple various ones of connectors points of one chip to various ones of connectors points of other chips. To avoid the traces coming into contact with each other, the traces are routed in particular configurations. Traces can be routed through various layers, which are connected through vias, in order to avoid having traces contact each other. The substrate is connected to a connector, which may be attached to a motherboard, through goldfingers on a single edge connector.
A connector point on a single chip has been coupled to a connector point on more than one chip in the same relative layout position on the same side of a substrate through multiple branch traces, including those of substantially equal length from an intermediate connector point.
A substrate such as that used in the Pentium.RTM. II processor includes multiple layers. Each layer adds complexity and expense. Further, the addition of vias adds complexity (for example by blocking trace routing channels) and expense.